(1) Field of the Invention
The present invention relates to a semiconductor memory device having a circuit for reducing the frequency of refresh cycles in data retention mode. It relates more particularly to a semiconductor memory device having reduced power consumption due to a reduction of the frequency of refresh cycles in data retention mode, but wherein decrease in boosting level of word lines that may occur by the reduction of frequency of the refresh cycle is prevented.
(2) Description of the Prior Art
Semiconductor memory devices are generally divided into a Read Only Memory (ROM) and Random Access Memory (RAM).
RAM includes Static RAM (SRAM) the memory cells of which are formed by flip-flops, each typically made up of four to six transistors; Dynamic RAM (DRAM) the memory cells of which are formed by transistor-capacitor combinations; and Pseudo-SRAM (PSRAM) which uses DRAM-type memory cells each with one MOS transistor and one capacitor, but the peripheral circuits of which have the same structure as the SRAM.
In random access memory, such as DRAM and PSRAM, where memory cells consist of one transistor and one capacitor, data stored in the memory cells decay with time. Accordingly, there is a need for a process of periodically refreshing (in what is commonly referred to as "refresh cycles") the memory cells in order to prevent the data from decaying.
A refresh process is similar to a conventional read/write operation. That is, a refresh cycle is carried out by reading out the data out of the memory and writing it back into the memory.
In prior art semiconductor devices such as DRAM and PSRAM which need refresh, the frequency of refresh cycles is the same in normal access mode and data retention mode (also known as self refresh mode). If the frequency of refresh cycles can be reduced in data retention mode, power consumption of the refresh circuit of the semiconductor memory device is reduced. In reducing the frequency of refresh cycles for achieving the above-identified advantage, the number of memory cells to be refreshed at one time may have to be increased as a function of reduction of the refresh frequency. As a result, the boosting level of word lines may decrease and result in deterioration in sensing margin of bit lines.